Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture with sum-of-products logic, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs).
The input/output function of the IOBs, the logic performed by the function blocks, and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs or interspersed with the columns of CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. The CLBs, IOBs, and interconnect lines are configured by data stored in a configuration memory of the FPGA.
PLDs have become popular for implementing various logic functions in electronic systems that, in the recent past, were typically implemented by smaller (<100,000 gates) application specific integrated circuits (ASICs). Such functions include glue logic, state machines, data bus logic, digital signal processors and protocol functions, for example. Early PLDs often provided insufficient capacity to implement these functions, so the significant investment of time and money to design, layout and fabricate an ASIC for these functions was justified.
However, recent advances in semiconductor and PLD technologies have produced PLDs with the necessary speed and capacity to implement these functions in most applications. Because PLDs are relatively inexpensive and can be programmed in as little as a few hours, the expense associated with the design, layout and fabrication of ASICs has become harder to justify. Further, the reprogrammability of many PLDs makes them even more attractive than ASICs because it is possible to update (reconfigure) PLDs, whereas ASICs must be replaced and expensive new masks generated for the new ASIC designs.
The versatility of reprogrammable PLDs is advantageous in applications such as aerospace, where remote reconfiguration is preferred over physical replacement. However, many aerospace applications expose components to environments where radiation is present, which can cause an error in a PLD known as a single event upset (SEU). A radiation environment contains charged particles that interact with silicon atoms. When a single heavy ion strikes a silicon substrate it loses energy through the creation of free electron hole pairs. This results in a dense ionized track in the local region, generating a current pulse that can upset the circuit. This is known as a single upset event. When a SEU occurs, the result may be transient or permanent.
Reprogrammable PLDs are configured with memory cells that determine how the device will configure each CLB. When a single particle hits a configuration memory cell, the resulting current pulse can trigger a transistor of the configuration memory cell to pass current and invert the value stored in the memory cell. This is referred to as a permanent configuration fault, because the configuration value within the memory cell will remain incorrect until CLB memory is reconfigured. Depending on the logic hit, the generated error may cause permanent variation in the performance of the circuit until the PLD is reconfigured. PLDs are often configured with circuitry to detect whether configuration memory has been altered and recover from the error.
A transient fault occurs when a SEU event generates a current pulse in a signal line. The variation caused by a transient faults following the particle strike will often propagate through the device logic and disappear in a time depending on the logic delay of the circuit. However, in some instances, a transient fault may cause circuits that operate in a plurality of states, such as a digital clock manager (DCM), to enter an incorrect state of operation. When this occurs, the circuit will produce incorrect output until it is reset to the proper state.
Previous techniques to detect and recover from transient SEUs involve the use of triple modular redundancy (TMR). In these techniques, three redundant circuits are implemented in parallel. The outputs of the redundant circuits are compared by a majority voter to detect transient SEUs. The compared value determined to be in the majority is used as output of the circuit to ensure continued correct operation. However, if the state of one of the redundant circuits has changed, TMR cannot provide for fault detection and recovery from additional SEUs unless correct operation of all redundant copies has been restored. To restore SEU fault protection, previous techniques perform a reset of the circuit producing a value in the minority of the compared outputs whenever a discrepancy is detected.
However, a reset does not provide immediate restoration of SEU fault protection. A reset may take several clock cycles to clear and set the circuit to the proper state. By performing a reset when transient faults occur that have not resulted in a change of state, previous TMR techniques unnecessarily place the TMR system into an unprotected state while the reset is being performed.
The present invention may address one or more of the above issues.